Safety Critical Design
我们严格的开发流程和先进的ASIC和FPGA设计工具可以帮助您在不影响性能的情况下实现目标，safety,and security.导师可以帮助您开发设备以满足DO-254quality objectives and government standards for reliability,durability,和效率。需求驱动的开发提供了从系统规范到硬件流程的连续性，including hardware definition,通过验证和合成进行RTL编码。
- Efficient and compliant electronic hardware development and verification
- Extensive control and reporting for project management
- Consulting,金宝搏娱乐城training and partners provide support
A high-assurance design process needs evidence that a design performs its intended function,as specified by the requirements.Mentor's solution for efficientrequirements management and traceability with ReqTracer，ensures that all requirements are met throughout the various development stages.Automating these capabilities allows you to validate that your implementation meets your requirements – ensuring product quality – in a cost-effective manner.Learn more about ReqTracer
- Link common applications such as DOORS,documents,or spreadsheets to detailed requirements within the hardware design and verification processes
- Choose granularity (level) of linking/tagging
- Perform"影子tagging of code so as not to modify code from previous design projects
- 相遇DO-254简单的可追溯性目标，complete and automated manner
- Provide necessary documentation to support design reviews and audits
A text editor and a design development environment have significant differences.HDL设计器是一个设计开发环境，帮助我们的航空和国防客户创建高保证设计。It streamlines team design needs,automates code quality checking,and enables practical reuse supporting a repeatable methodology.HDL Designer提供配置和版本管理功能，下游集成确保整个设计开发的效率。
- Process Control:Enforces coding style,supports file and version management,并保持模拟和合成的下游结果。
- 代码质量检查：Delivers a customizable RTL rule checker for linting and downstream code preparation.
- 可视化：Generates block diagrams and other design visualizations to help team members understand code structure and function.
- Documentation:Automatically generates documentation in HTML or Microsoft file formats.Dynamic updates or documents for reporting are easily created from the actual design files to ensure comprehensive and complete information.
- 配置管理：Project-based design development ensures libraries,为保持一致性和存档，包含了设计文件和相关文件。
- Review support:Supports preparing for,conducting,and documenting the design for project reviews.
- Any Silicon
- Any Vendor
Actel,Altera,爱特梅尔ChipExpress,Lattice,Xilinx,plus any ASIC foundry
- Any Language
Integrated with all leading Simulation,模拟和正式解决方案。Integrated with all commercial synthesis and P&R environments
Verifying that a device performs its intended function (and does not do anything unintended) is a crucial part of safety-critical design and required in yourDO-254流动。Mentor's industry-leading verification solutions support the most complex designs.不管你目前的方法如何，如果你在实验室或验证上花费了太多时间，Mentor has solutions that can help improve your verification efficiency and end-product quality.
- 模特儿is the industry standard simulator in the mil-aero industry.您可以在流的早期运行测试来模拟设计的行为，catching bugs much earlier than you would if you waited for lab testing.ModelSim还包括代码覆盖率，which you must run as part of elemental analysis if you are doing DAL A/BDO-254projects.Learn more about ModelSim
- Questabuilds on ModelSim's strong simulation engine with a verification platform that provides modern verification methods for complex designs with multiple functions and concurrent behaviors.These methods include assertion-based design and assertion debugging,交易级刺激，约束随机测试生成，functional coverage and verification management (with automated links back to requirements).Learn more about Questa
- FormalPro是逻辑等价性检查工具，用于在合成后和路由后验证逻辑网络列表。Netlist comparison back to the golden RTL code identifies defects and provides superior coverage to simulation while executing 100x faster than netlist simulation.FormalPro supports FPGA and ASIC flows.Learn more about netlist verification with FormalPro
A high priority for safety-critical andDO-254flows is that the synthesis results are repeatable and generated with design assurance in mind.Precision Synthesis提供独立于供应商的综合，确保可靠的设计操作和安全的FSM编码，radiation-hardened device support,optimization control,integration with FormalPro for logical equivalency checking (LEC),and efficient design re-use for any FPGA device.Learn more about Precision Synthesis
If you are suffering from process inefficiencies – especially pertaining to verification methodology – and need to reduce the cost ofDO-254programs,Mentor experts can perform a方法论评估你的设计流程。它们将为您提供一个安全、渐进地向更现代化、更高效的设计流程移动的计划，并着眼于DO-254compliance.
- Reduced implementation cost ofDO-254
- Risk mitigation of schedule slips or budget overruns
- Incremental improvements to your current methodology
- Proven process – used on over 50 projects
- Recommendations targeted to your unique methodology,goals,形势
Mentor Consultinghas extensive experience helping aerospace and military companies improve their methodology,achieveDO-254compliance,accelerate success,and reduce risk,尤其是在新的验证方法和测试台的创建中。我们直接与您的设计和验证团队合作，评估他们的验证需求，architect a verification environment,help you implement a solution,协助规划和管理。Our consultants are experts in SystemVerilog-based verification using Mentor's OVM methodology and advanced verification tool suite.了解有关导师咨询的更多信息
Simplifies,automates & enables requirements traceability from specification of the hardware specification through HDL coding,实施与验证。
Design creation/RTL Reuse and management environment for FPGA and ASIC design that incorporates all the features of the following tools and more
ModelSim combines high performance & high capacity with the code coverage & debugging capabilities required to simulate larger blocks & systems
Questa® Advanced Simulator
Combines high performance and capacity simulation with unified advanced debug and functional coverage capabilities for the most complete native support of Verilog,SystemVerilog,VHDL,SystemC广域网，UPF and UVM.
Questa® CDC Verification
Questa CDC is the industry's most comprehensive and easy-to-use clock-domain crossing verification solution
Superior quality results,屡获殊荣的分析，以消除缺陷和先进的操作员推理，使FPGA供应商独立设计。
FormalPro is the equivalence checking solution for gate-level regression testing of FPGAs and ASICs of 100,000门或更多。