Tessent PLLTest

Tessent® PLLTestprovides complete,parametric,embedded test for PLLs,DLLs,and clock signals.It can measure jitter,phase delay,duty cycle,frequency ratio,lock time,and lock range,all in less than 100 ms,including test set-up and on-chip comparison to test limits via the IEEE 1149.1 TAP interface.

Tessent PLLTest uses the Mentor Graphics unlimited time-resolution analysis (ULTRA) patented technology.One 4k-gate ULTRA module can test any number of PLLs,and a TAP controller (or IEEE 1500 WTAP) can interface to any number of ULTRA modules.

Features and Benefits

  • Jitter measurement with picosecond accuracy: Histogram or RMS,timing jitter (loop bandwidth sensitive),period jitter (VCO noise sensitive).
  • Phase error and duty cycle measurement with picosecond accuracy: Any number of outputs,any synchronous output frequency.
  • Lock time measurement: Any frequency deviation,single clock-cycle accuracy.
  • Design and test automation: RTL insertion and testbench generation,characterization and production tests,repeatability analysis.

Related

Tessent SiliconInsight®

Tessent PLLTest includes Tessent SiliconInsight Mixed-Signal solution.With this interactive capability,any of the supported PLL embedded tests can be instantly run on a PC or tester.Tessent SiliconInsight

Tessent 金宝搏娱乐城Training

We have 金宝搏娱乐城training courses available for Tessent products in our training centers around the world,online,or at your site.Tessent 金宝搏娱乐城training courses

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