Tessent® DefectSimis a transistor-level defect simulator for analog,mixed-signal (AMS),and non-scan digital circuits.It measures defect coverage and defect tolerance.Tessent DefectSim is perfect for both high-volume and high-reliability ICs.
Tessent DefectSim replaces manual test coverage assessment in AMS circuits needed to meet quality standards such as ISO 26262 and provides objective data to guide improvements in DFT.Tessent DefectSim dramatically reduces SPICE simulation time compared to simulating every potential defect.
Features and Benefits
- Measures likelihood-weighted coverage of defects in AMS circuits.
- Guides test time reduction without reducing quality
- Guides increases in test coverage of defects in AMS and custom logic circuits.
- Guides improvements in tolerance to manufacturing defects or latent defects.
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Analog Benchmark Circuits
To aid general improvement and comparison of mixed-signal DFT methods and tools,including analog fault simulation,a set of analog,mixed-signal,and digital circuits are available for free.The initial cells were created by ams AG and Mentor.Additional contributions that use the same process files and operating conditions are welcome.Address any correspondence firstname.lastname@example.org.
Version 2.0 includes:
- CMOS process device models,including typical and 4 corners,derived from ams's 350 nm process
- SPICE netlists for 9 commonly used analog and mixed-signal functions (6 complex functions and 3 transmission gates)
- SPICE netlists and Verilog models for 42 basic combinational and sequential logic gates
- Testbenches for the functions and gates,including specifications with limits for operation at 3.3V,27C
Version 2.1 includes:
Same files as Version 2.0 plus:
- SPICE netlists for two additional circuits: PLL and ADC
- Schematic diagrams for each A/MS netlist
- List of potential defects for each A/MS netlist,with area-based likelihoods
- For BANDGAP1,collapsed parallel transistors into single transistors,each with increased m (multiplier),consistent with IEEE P2427 proposed rules
- Updated README file
Version 2.2 includes:
Same files as Version 2.1 plus:
- SPICE netlist for one additional circuit: VREG
- Corrected models for several logic gates in LOGIC.v
- Corrected BANDGAP1,OPAMP1,and PLL1 testbenches
- Specifications and additional testbench for the op-amp and comparator
- Updated README file
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