Calibre 3DSTACK

Calibre 3DSTACK extends Calibre die-level signoff verification to enable complete signoff verification of a wide variety of 2.5D and 3D stacked die assemblies.使用Calibre 3dstack,designers can perform signoff DRC and LVS checking of complete multi-die systems at any process node without breaking current tool flows or requiring new data formats,significantly reducing time to tapeout.Because 3DSTACK is enabled using standard Calibre DRC,Calibre LVS and Calibre DESIGNrev license features,no new licenses or tools are required.

Calibre 3DSTACK In-Depth

While standard Calibre product offerings support foundry-qualified design rule checking (DRC) and layout vs.schematic (LVS) comparison of individual dies,Calibre 3DSTACK extends Calibre die-level signoff verification to enable complete design verification of stacked die assemblies.Calibre 3DSTACK can be used for verification of a wide variety of stacked die assemblies,such as stacked memories,stacked sensor arrays,interposer-based structures,or package-level routing (wafer-level packaging).

Based on package information in a rule deck (die order,x/y position,rotation and orientation,etc.),Calibre 3DSTACK performs all DRC and LVS checking on the interface geometries between chip designs,including bumps,balls,through-silicon vias (TSVs),or copper-to-copper bonding,and can support dies from multiple processes with ease.

Traditional DRC and LVS verification tools assume layers are co-planar,and that polygons located on the same GDSII layer are physically located on the same vertical plane.2.5D and 3D structures contain multiple die that potentially contain polygons on the same GDSII layer,but at different vertical depths,and quite possibly representing completely different geometries.When 2.5D and 3D designs are verified with traditional tools,layer conflicts can appear to exist between multiple dies with the same layers.

Calibre 3DSTACK uniquely identifies geometries per layer per die placement in the assembly,allowing accurate checking between dies.By supporting flexible stacking configurations of multiple dies,Calibre 3DSTACK minimizes disruption to existing verification flows while providing designers with maximum flexibility across process nodes and stacking configurations (interposer-based and full 3D).With the ability to differentiate the layers of interest per individual die placement,Calibre 3DSTACK enables designers to verify the physical attributes (offset,scaling,每个模具的旋转等,while also tracing the connectivity of the interposer or die-to-die interfaces.Calibre 3DSTACK also provides extensibility,with the capacity to incorporate new extraction and verification solutions in the future.

3d stack

Calibre 3DSTACK enables signoff verification of chip stacks with flip chips,silicon interposers,through-silicon vias,还有更多。

3d stack

Calibre 3DSTACK uses information supplied in the rule deck to support the various stacking configurations.

3d stack

Typical 2.5D and 3D configurations that Calibre 3DSTACK can support.

3d stack

Calibre 3DSTACK verifies that micro-bumps physically align and that there is proper electrical connectivity through die interface.


  • Supports all types of stacked designs,including interposers,stacked memory,front-to-back TSV configurations,package-level routing,and more
  • Supports multi-process configurations without the need for foundry-specific process rule files
  • Enables connectivity tracing of passive interposers to identify shorts or opens
  • Provides system netlist generator tool for creation of assembly source netlists or full assembly extracted netlists
  • Extends existing Calibre licenses
  • Included in TSMC CoWoS and InFO reference flows


  • No new Calibre licenses or tools required
  • Accurate DRC and LVS signoff verification of 2.5D and 3D assemblies
  • Applicable to virtually any stacked design configuration
  • Ensures signoff Calibre verification while reducing time-to-tapeout


""Tezzaron specializes in 3D wafer stacking and TSV processes.We work with dozens of customers to create custom 3D-ICs for prototyping and commercialization,including recent 3D-ICs in 40 nm and 65 nm,the first at these small nodes.By collaborating with Mentor Graphics,we can offer our mutual customers a comprehensive design verification solution.It creates the highest value for them with the least disruption to their existing flows.使用口径,our customers get the best possible turnaround time.Even better,there is no need to generate a ‘Frankenstein' GDS file combining all the individual dies in a 3D-IC assembly,and no need to deal with a ‘monster' rule file combining different die processes.口径使过程非常快速和相对容易。""

Robert Patti,CTO and VP of design engineering,Tezzaron Semiconductor

""TSMC is extending its 3D IC capabilities to provide designers with more technology choices as they develop new products.CoWoS provides a straightforward way to achieve reduced footprint and power for multi-die systems using different nodes or process types,while minimizing complexity and design cycle time.Mentor is providing various elements to the TSMC flow including design cockpits for both digital and custom designers looking to use TSMC's CoWoS offering.""

Suk Lee,senior director,TSMC Design Infrastructure Marketing Division

""Mentor has been our collaborator in physical verification for multiple nodes,and now that we are moving from single-die to multi-die systems,它们继续为新技术的发展提供宝贵的贡献。""

Suk Lee,senior director,TSMC Design Infrastructure Marketing Division
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