Advanced SoC Debug Solution
Intuitive and powerful HW and SW debug solutions to improve debug productivity across ESL,formal,RTL /门电路级模拟和仿真平台
The Mentor debug solution maximizes performance,capacity and automation for the complete SoC design and verification cycle.Tightly integrated with Questa Simulation and Veloce Emulation,the solution includes the industry-leadingCodelinkproduct family for hardware and 金宝愽备用网址software debug,and the new可视化工具调试环境for testbench and hardware debug.
- 提高嵌入式软件的调试效率，transaction-level,测试台，RTL,gate-level and low-power design and verification
Certus™ Silicon Debug
Certus enables debugging system- and chip-level issues by enabling efficient instrumentation of 1,000's of signals with the ability to capture very deep traces.Easy 金宝愽备用网址software-driven run-time configurability...
Verification Horizons Blog
An online forum to provide updates on concepts,values,standards,帮助理解高级功能验证技术可以做什么以及如何最有效地应用它们的方法和示例。
Part 11: The 2018 Wilson Research Group Functional Verification Study
ASIC/IC Low Power TrendsThis blog is a continuation of a series of blogs related to the 2018 Wilson Research Group Functional Verification Study (click here). In my previous blog (click here),I presented...View Blog Post
It Don't Mean a Thing … Without Methodology
Okay,so not nearly as catchy a title as the inspiration,but it's something I've been thinking about as I've been preparing to attend DVCon next week.At the end of the day,it's really methodology that...View Blog Post