Questa® Formal Verification


The Questa® Formal Verification tool complements simulation-based RTL design verification by analyzing all possible behaviors of the design to detect any reachable error states.This exhaustive analysis ensures that critical control blocks work correctly in all cases and locates design errors that may be missed in simulation.

Questa Formal Verification can be used as soon as the design is complete to debug blocks before integration,and to find potential errors long before simulation test environments are available.Sharing a common language front end with the Questa Simulator and leveraging the integration with the Unified Coverage Database (UCDB),Questa Formal Verification is the perfect tool to accelerate bug detection,error correction and coverage closure.


How Questa Formal Verification Works

Questa Formal Verification analyzes the behavior of the design to identify all design states that are reachable from the initial state.This analysis allows Questa Formal Verification to explore the whole state space in a breadth-first manner,in contrast to the depth-first approach used in simulation.

Questa Formal Verification is therefore able to discover any design errors that can occur,without needing specific stimulus to detect the bug.这可以确保验证的设计在所有合法输入场景中都是无缺陷的。At the same time,this approach inherently identifies unreachable coverage points,这有助于加快覆盖率的关闭。

Automatic Push-Button Solutions

Questa Formal Verification solutions provide easy-to-use,next generation automatic applications for checking many common design errors.For example,the Questa X-Check solution uses formal algorithms to exhaustively solve the twin problems of X-optimism and X-pessimism that occur due to X-values (unknown signal levels) in designs;finding bugs (errors) that would not have been found with traditional simulation-based verification technology.

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