C/C++/SystemC HLS

Catapult is the only High-Level Synthesis Platform to natively support both ANSI C++ and SystemC,给设计师以他们喜欢的语言工作的自由,并提升到一个更高效的抽象级别。弹射器合成的抽象模型通常需要减少80%的手写代码,最多可以模拟1个,000 times faster than synthesizable RTL.

From these high-level descriptions,Catapult generates optimized Verilog or VHDL,ready for production RTL synthesis and verification flows.The platform gives designers control over which regions are optimized and the ability to work top-down or bottom-up,这是RTL IP集成所必需的。

The database and smart caching techniques provide at least a 10X capacity improvement,making the synthesis of large subsystems possible.The synthesized RTL is optimized for power,performance,面积,and timing closure.这个经过验证优化的RTL代码已经准备好部署到企业验证方法中。包括基于uvm的流。


  • Native dual-language support of SystemC and C++
  • 在复杂设计上实现设计关闭所需的控制和可预测性
  • Comprehensive design management and assembly systems with 10X capacity
  • 与标准功能验证方法的集成
  • Verification-optimized RTL code

Thales Alenia Space France

"With Catapult 8,we can now efficiently synthesize our multi-million gate data processing hardware.我们写的是C++或SystemC,根据每个项目的设计和验证需求,and then use Catapult's configurable hierarchy technology,which makes it possible to synthesize much bigger designs.""

伊曼纽尔·李珍,Head of ASIC/FPGA Design Group,Thales Alenia Space France


"Catapult 8 allows rapidly evolving C++ algorithms to be explored and optimized to meet our area,power and performance goals.With these capabilities and our successful experience with HLS,we have decided to migrate new IP development into synthesizable C++ to more efficiently reuse and retarget our IP.""

Michael Giovannini,Hardware Project Leader in Front-End Team of Consumer Product Division,STMicroelectronics

"After Evaluating Catapult for high-level synthesis,我们发现可以缩短初始设计师的设计时间,因为弹射器图形用户界面非常容易和直观的使用。We also found that Catapult would give us both the quality and productivity we needed,我们能够在很短的周转时间内开发出非常复杂的IP,将其包含在我们的ASIC中。”"

Tetsuya Kawasaki,Deputy General Manager SOC Technology Department of R&D Division,Olympus


"As Catapult earned our trust through predictable functional accuracy and high quality of result,we gained the needed confidence to assign bigger designs to the tool,resulting in even larger productivity gains.""

Alexandre Cellier,STMicroelectronics


"With the Catapult flow,RTL debug literally disappears.C模型在其环境中得到验证,and from there correct-byconstruction RTL is created.This reduces the verification effort dramatically.""

Giuseppe Bonanno,STMicroelectronics

Chat| Contact